GLS Verification Environment Development

It has already been proved that GLS is not avoidable in most of the SOC verification and also described associated difficulties and their resolutions. Here instead of discussing about importance of GLS the focus is on development of GLS environment which is very crucial part of any GLS simulation. It is assumed that RTL functional verification environment is already exist and now we need to upgrade the same environment for Gate Level Verification

Introduction to Simulation & Back Annotation

1- Simulation without timing(Without Back Annotation)

2- Simulation with Back Annotated Timing

3-    Back Annotation

        Verilog allows us to mention “path delays”, “timing checks” and “specparam” constants via a special code block called the specify block. The simulator will utilize back-annotation in conjunction with these specify blocks described in component library(Generally specify block added in primitive[UDP] description of the cell or component used in netlist). SDF files contain timing values for specify path delays, specparam values, timing check constraints, and interconnect delays. The timing values in SDF files usually come from ASIC delay calculation tools that take advantage of connectivity, technology, and layout geometry information. SystemVerilog back-annotation is the process by which timing values from the SDF file update specify path delays, specparam values, timing constraint values, and interconnect delays. When the simulation continues with back annotation system task "$sdf_annotate" all those path delays and timing checks in the specify block will be updated with the timing information from the SDF file.

4- Standard Delay Format

      “ The Standard Delay Format (SDF) was designed to serve as a simple textual medium for communicating timing information and constraints between electronic design automation tools. The Standard Delay Format (SDF) is an existing OVI standard for the representation and interpretation of timing data for use at any stage of the electronic design process. The ASCII data in the SDF file is represented in a tool and language independent way and includes path delays, timing constraint values, interconnect delays and high level technology parameters. This standard describes the IEEE version of the SDF standard.

              

   

Input Needed for GLS Simulation

1- Gate Level Netlist files

a-Netlist should have passed equivalence check(Formality Clean)

2- Gate Level Simulation Library (for example udp library of components)

3- SDF (Standard Delay Format) corresponding to min and max corner

a- Check whether SDF includes post layout interconnect delays

b- The delay format should be proper. All values for min/typ/max should be present in SDF. If not, the suitable option should be provided with compiling option. (For example with VCS If value for typical delay is missing then we need to use +max/min_delay switch with compilation).

c- SDF should be consistent with the design netlist for simulation. Otherwise will get error during annotation (same design hierarchies and port list should be present)

d- SDF should also be consistent with the timing models of cell: 

    An SDF file contains only timing data. It does not contain instructions to the analysis tool concerning how to model the timing properties of the design. The SDF keywords and constructs that surround the data in the file describe the timing relationships between elements in the design only so that the data can be identified by the annotator and applied to the timing model in the correct way. It is assumed that the timing models(specify block in UDP or definition of the cell) used by the design are described to the analysis tool by some means other than the SDF file. Thus, when using SDF, it is crucial that the data in the SDF file be consistent with the timing models. 

    For example, if the SDF file identifies an occurrence of a 2-input NAND gate ASIC library cell in the design and states that the input-output path delay from the A input to the Y output is 0.34ns, then it is imperative that the timing model for this cell has an input port A, an output port Y and that the cell’s delays are described in terms of pin-to-pin delays (as opposed to distributed delays or a single all-inputs-to-the-output delay).  

4- SDC (Synopsys Design Constraints) corresponding to min and max corner

5- Test bench for Functional Simulation

Testbench Update needed for Gate Level Simulation

1. RTL files to be compiled for functional simulation should be replaced with netlist(.v) files for GLS.
2. Copy suitable libraries(udp or other form) to one place which contain component definitions used inside netlist(Gate Level Design). These component definition also include specify block with timing information.
3. Provide simulation tool a visibility to access library path using suitable format.
4. Copy SDF file to working location.
5. Add the SDF annotation command to the elaboration option wrt to simulation tool used and along with the associated SDF file location (for example if VCS is used : -sdf max:TOP_DUT_NAME:max_sdf_file_path)
6. Generally analog modules in the design have behavioral model instead of netlist and if SDF includes these analog modules, then replace these analog module instances with some dummy module name so that it will discard timing check for analog modules.
7. Get double, triple or quadruple synchronizer flop list with the help of STA tool
8. Force all notifiers* of the sync flops to x in the simulation(This may also specific to the tool used. The idea is that similar concept should be implemented with suitable options specific to other tool and supported library so that timing violations should not be reported for these flops).
9. Find out the non resettable FFs which are initialized with x at the time of reset from the netlist and force the output of these FFs to some random value either 0 or 1. Please read tool specific manual "how to find out these FFs". Also one can refer "Identification of non-resettable flops for faster Gate Level Simulation" SNUG 2010 for more detail.
10. Compute the input delay from the max/min sdc(Synopsys Design Constraints) file and apply these delays to their corresponding primary inputs in top testbench file.

Note1:

Please check if some signal name got changed(in the netlist) from old signal name present in functional TB and giving cross module reference error. If getting errors then check the new signal name from the netlist hierarchy and replace with the new signal name in TB along with the suitable GLS switch

Note2:

Please cross check from log file that netlist files got properly compiled and also verify whether SDF get annotated with error and warning messages in the end. Check and confirm these errors with synthesis guy and designer whether to discard or not. 

*Notifier

Notifier is a register whose value VCS toggles when there is a timing violation In a Timing Simulation, a register will output an X when a setup or hold violation occurs on the register. This X will propagate through the simulation and often cause the simulation to fail. Typically, the solution is to fix the timing problems in the design that cause the violation to occur. In certain cases, however, asynchronous portions of the design might exist in which these violations cannot be avoided. X propagation must be disabled in these situations.

The built-in timing checks for Verilog and SystemVerilog setup and hold time checks ($setup,$hold, and $setuphold) have an optional notifier output. This notifier output toggles from 0-1-X-Z whenever a timing violation is detected. Most ASIC and FPGA flip-flop models are built from Verilog User Defined Primitives (UDPs) and the notifier signal is typically listed as one of the inputs to the UDP table. Whenever the notifier input toggles (caused by a timing violation), the flip-flop output goes unknown and that unknown is what is visible on the output of the gate-level flip-flop models. The notifier on these first-stage flip-flop models can be force to a logic level to prevent them from toggling and causing the flip-flop outputs to go unknown during simulation.

One clever technique used is to forces the timing violation notifiers of the first-stage synchronizer flip-flops to be forced to one logic level so they can never toggle and trigger X's into the flip-flop models